The present invention relates to electronic clock signal generation, and more specifically to a system and method for adjustably multiplying an input clock signal to obtain a digital output clock signal having a shorter cycle time.
Phase locked loops and frequency locked loops are often used to multiply a lower frequency signal up to a higher frequency. However, such circuits require analog voltage controlled oscillators and other components which are not easily integrated within a primarily digital logic integrated circuit, making their cost and power consumption undesirable in all but a few cases where precise analog tuning is required.
There exists a need for an adjustable digital clock multiplier which is easily incorporated into a single, digital logic integrated circuit. In such way, area and power savings may be achieved.
Accordingly, an adjustable clock signal multiplier is provided for generating an output clock signal having a selected cycle time which is shorter than the cycle time of an input clock signal. The clock signal multiplier includes a pulse generator which is responsive to input including an input clock signal to output a pulse. A programmable delay circuit is coupled to receive and delay the pulse, and is further coupled in feedback relation to the pulse generator to provide the delayed pulse as input thereto, whereby the pulse generator acting together with the programmable delay circuit outputs a train of pulses in response to the input clock signal. A counter is adapted to be incremented based on the train of pulses and is reset in response to the input clock signal. The clock multiplier further includes a limiter which is adapted to adjust a time delay of the programmable delay circuit in response to output of the counter. A longer delay reduces the number of pulses in the output clock signal; a shorter delay increases the number. In this manner, an output clock signal is obtained which has the selected cycle time.
A method is provided by which an input clock signal at an input clock cycle time is multiplied to obtain an output clock signal having a selected cycle time which is shorter than the input clock cycle time. The method includes generating a pulse in response to the input clock signal. The pulse is then delayed by a certain time delay. A second pulse is generated in response to the delayed pulse and that second pulse is also delayed. This process may then be repeated from zero to a plurality of times within the input cycle time to generate a train of pulses which include at least the first and second pulses and perhaps more. Based on the number of pulses in the pulse train, the time delay is adjusted and the above process of generating and delaying pulses repeats until an output clock signal is obtained which has the selected cycle time.